Time
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Ballroom A
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Ballroom B
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Ballroom C
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8:30~9:00 |
Registration |
9:00~9:10
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Opening |
Chin-Lung King, President, Grand Technology |
9:30~10:10 |
Artificial Intelligence Verification-The Future of Chip Verification |
The new game after chip war |
Shift-Left Design Closure Methodology on SDC |
激發IC設計革命狂潮! 探討人工智慧驗證—未來的晶片驗證趨勢 |
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SDC驚人技巧加速設計收斂,突破極限時序的加速方法解析! |
Truechip |
KC |
Excellicon |
10:20~11:00 |
Semitronix Big Data Analytic Platform for smart manufacturing & design house |
Using AI to Design Chips - AI-assisted Floorplan Solutions |
Cyber-physical security from chip to cloud with PQC (Post-Quantum Cryptography) |
Semitronix革命性的大數據分析平台,為智慧製造和設計公司帶來巨大的突破! |
通過人工智能協助晶片的布局擺置設計 |
使用 PQC(後量子密碼學)實現從芯片到雲端的網絡物理安全來改變全世界 |
Semitronix |
MAXEDA |
Secure-IC |
11:10~12:00 |
3D fullwave EM with DC-mmWave-TeraHz accuracy for IC and 3DIC designs |
Improve circuit design efficiency and quality with MunEDA ML-based EDA tools for migration, sizing & verification |
Holistic Approach to Pre-Silicon Verification of Complex SoC and RISC-V Emulation Case-study |
適用於 IC 和 3DIC 設計的具有直流至毫米波 TeraHz 全波段高精度的 3D電磁模擬器 |
MunEDA- AI學習與最佳的自動化驗證 |
創新的綜合性方式讓Pre-Silicon 驗證在複雜的SoC及 RISC-V 模擬上變得更容易更精確 |
Lorentz |
MunEDA |
Aldec |
12:00~13:30 |
Lunch Time |
13:30~13:40 |
Lucky Draw (Ballroom B) |
13:50~14:30 |
StarVision PRO -- SoC, Multi-mode Debug for Transistor, RTL, and System-Level Designs |
Wide Bandwidth Analog-to-Digital Converter in Samsung LN08LPP with a novel time Interleaving algorithm to achieve performances suitable for 5G applications |
Multi-certified security technologies and application in Automotive, lightweight and high performance systems
|
StarVision® PRO-最直觀的Netlist轉schematic探索工具,快速鎖定電路並加速除錯 |
5G尖端之選-搭載全新時序交錯演算法的寬頻類比數位轉換器 |
通過多項認證技術徹底改變您的汽車安全性 |
StarVision |
Vervesemi |
Secure-IC |
14:40~15:20 |
Design adaptive eFPGA IP. The benefits of programmable logic without pain |
Altair FlowTracer - Mission-Critical Dependency Management |
How to be protected from Side-Channel Attacks? FIPS 140-3 compliance and hardware trojan detection |
讓Menta的eFPGA 釋放可編程邏輯的力量 |
高效的流程管理,掌握細節確保計畫順利執行 |
FIPS 140-3:晶片安全威脅的終極解決方案來抵擋防不勝防的側信道攻擊! |
Menta |
Altair |
Secure-IC |
15:30~16:10 |
Data Driven IC Yield Enhancement Solution |
SoC Floorplan Exploration System |
Soft Error analysis and mitigation for high reliability application |
挖掘數據潛力,助您提升IC良率的革命性解決方案 |
Design Plan –創新的晶片模塊布局探索工具 |
|
Semitronix |
MAXEDA |
IROC |
16:20~17:00 |
|
Sustainability: Building Collective Well-being
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|
Sharon Chuang |
|
17:00~17:20 |
Lucky Draw (Ballroom A) |
17:20 |
Wrap up |