Speaker:

 

 

Subject:  Full-chip Timing Variation Signoff

 

Abstract: 

Process variation library models in the Liberty Variation Format (LVF) have become commonplace in timing signoff for standard cells, yet the embedded memories and mixed-signal blocks that comprise most of the chip area still employ library modeling methodologies from several technology generations ago.

This paper explores the underlying reason for this modeling gap, highlights the inefficiencies in existing methodologies, and demonstrates how a new characterization system can overcome these hurdles and bring forth accurate timing variation signoff to the entire System-on-Chip (SoC).

 

Target Audience: Timing team, CAD team, memory and block designers