Speaker: Charles Li

Charles possesses a strong background in semiconductor circuit design,
having worked early in his career as an APR engineer, accumulating rich experience in front-end design and implementation.
Currently a Senior Layout Engineer at Silicon Tubes Technology,
He has long been involved in advanced process layout planning and design optimization, possessing a complete and comprehensive understanding of the chip development process.
With his diverse experience spanning circuit design, APR, and layout implementation, Charles can approach problems from different technical perspectives.
In this presentation, Charles will combine his practical experience to discuss the key challenges of high-speed circuit layout, guiding the audience to explore how to overcome layout bottlenecks from various angles.

Subject: Key Challenges of High- Speed Circuit Layout 

 

 

Abstract: 

I. High-Speed Circuit Development Trends
II. SerDes Key Architecture Analysis
III. High-Speed Circuit Layout Practical Techniques

 

Target Audience: