Speaker: Himanshu Bhatnagar

Over 20 years of chip design experience, designing complex SOCs in networking, communications, imaging, among others. Himanshu’s background and experience involving SOC realization resulted in publication of his book; “Advanced ASIC Chip Synthesis: Using Synopsys Design Complier and Primetime” as a practical guide to synthesis and static timing analysis. Prior to Excellicon, Himanshu served as an advisory board member of several EDA companies.

 

Subject: Shift-Left Design Closure Methodology
(超越不可能! SDC驚人技巧加速設計收斂，突破極限時序加速)

Abstract: 
As chip sizes grow, the need for discovering all the issues as soon as possible becomes critical. Issues discovered during physical design may impact the RTL whereby the RTL needs to be modified. This causes immense challenges to the entire design cycle and often leads to significant delays. We will introduce a shift-left methodology to address these challenges. The author will present a flow spanning RTL design, RTL power reduction techniques, RTL floorplanning, Clock Tree exploration, and finally timing constraints.

 

Target Audience: SoC Frontend and Implementation Engineers