Time	Ballroom A	Ballroom B
8:30~9:00	Registration
9:00~9:10	Opening
	Chin-Lung King, President, Grand Technology
9:15~9:50	Designing PCBs faster and better with JITX's E Next-Gen EDA Tool: An Introduction and Update	The New Opportunity of AI from Edge Computing
	PCB設計革命！JITX 次世代EDA工具強勢登場與最新進展	AI 的新契機 - 邊緣運算
	JITX	Mr. KC Wu
10:00~10:35	NoC Silicon IP – The Critical Part of the Chip Ecosystem	LLM and Next-Generation EDA Tools for IC Manufacturing
	NoC矽智財 ─ 晶片生態系中的關鍵核心	機器學習和大模型在半導體製造大數據分析的應用
	Truechip	Semitronix
10:45~11:20	Born for 5G, AI, and Advanced Packaging — The Next-Gen EM Solution	Analog Mixed Signal Design with Machine Learning To Realise Self-Healing and Fail safe Chips
	為5G、AI與先進封裝而生 — 新世代電磁模擬解決方案	以機器學習實現自我修復的類比混合訊號晶片設計
	Lorentz	Verversemi
11:30~12:05	Accelerating AI System Development with Visual and Modular Tools	eFPGA and how to use it in real life applications
	讓AI 落地更簡單：模組化、視覺化的AI系統開發之道	eFPGA的彈性設計驅動 SoC智慧升級與實際的應用解析
	MICROIP   Dr. Wu	Menta
12:05~13:35	Lunch Time
13:35~13:45	Lucky Draw (Ballroom B)
13:50~14:25	Redefining Subsystem Verification & Debugging for UCIe and USB	Semitronix DFM Platform: Closed-Loop Yield Solution from Design to Production
	重新定義UCIe與USB子系統的驗證與除錯方法	Semitronix DFM 平台：從設計到生產的良率閉環協同優化解決方案—引領先進製程的躍進之路
	Truechip	Semitronix
14:35~15:10	High-speed IP layout techniques in advanced node	Bringing Security to Chiplets for Trusted Systems-in-Package
	高速IP在先進製程Layout的眉角	Secure-IC帶來串聯異質晶粒(chiplet)的信任機制，正面迎戰後量子時代的安全挑戰
	Sillicon Topology	Secure-IC
15:20~15:55	Altair Starvision Pro: Inspire novel EDA vision	Accelerating Product Development: Fast-Turn, High-Mix Advanced PCB Design for ODMs using JITX
	整合偵錯利器-開啟電路設計軟體的新篇章	ODM必備利器！JITX 助攻多元需求、高階 PCB設計與極速交付
	Dr. Irving Hsu	JITX
16:05~16:40	Data Acquisitions in the Modern Era : Challenges, Market Dynamics and Applications	Future Trends in Semiconductor Yield Management System
	現代資料擷取所面臨的挑戰、市場趨勢與應用實例	引領未來：半導體良率管理系統的AI智能革新與前瞻趨勢
	Verversemi	Semitronix
16:40~17:00	Lucky Draw (Ballroom B)