Speaker: Dr. Tung-Chieh Chen 

Tung-Chieh Chen received his B.S. and Ph.D. degrees in electrical engineering from National Taiwan University (NTU), in 2003 and 2008, respectively. He is a co-founder and Chief Executive Officer of Maxeda Technology since 2015. He was a visiting scholar at the University of Texas at Austin in 2007. He joined SpringSoft (2008-2012) and then entered Synopsys (2012-2015) by acquisition. Dr. Chen is a recipient of the 2021 Design Automation Conference Under-40 Innovators Award. He was the first place winner in the 2007 ACM SIGDA CADathlon Contest. He received the Best Dissertation Award from the Graduate Institute of Electronics Engineering (GIEE) at NTU in 2008, and the Electronic Elite Special Contribution Award from GIEE at NTU in 2017. He has published 12 IEEE Transactions on CAD journal papers, 26 IEEE/ACM conference papers, and 14 US patents, all on VLSI floorplanning and placement. Dr. Chen has served as a technical committee member for ISPD, ICCAD, ASP-DAC, and DAC.

 

1. Subject: Using AI to Design Chips - AI-assisted Floorplan Solutions
( 全新的探索式演算法－助IC設計做模塊擺置自動化與訊號整合最佳化 )
2. Subject : SoC Floorplan Exploration System
(Design Plan – 創新的晶片模塊布局探索工具 )

 

Abstract:  Using AI to Design Chips - AI-assisted Floorplan Solutions  全新的探索式演算法－助IC設計做模塊擺置自動化與訊號整合最佳化 

Generative AI has led to booming demand for high-performance chips which contain millions of components. And the optimized placement of which is difficult to achieve given the huge number of possible placement states.
Reinforcement Learning offers a solution, but it is still very challenging due to extensive runtime. Maxeda offers MaxPlace RL reward platform to achieve it 100 times faster. It has already passed the silicon-proven with better PPA by one of the top 10 fabless companies.

 

Target Audience: Physical designer, CAD    




Speaker: Michael Chang 

Bachelor, EE@DYU
Extensive experience in Semiconductor, LCD, LED, and PV industries
Sales Director/VP, GT Advanced Technologies, Heraeus, and iSTART-Tek

Abstract: Subject : SoC Floorplan Exploration System (DesignPlan –創新的晶片模塊布局探索工具)

 

In the design beginning stage, it’s always challenging to find a suitable SoC floorplan for all blocks to get better routing congestion and less wirelength. DesignPlan, the SoC Floorplan Exploration System is the 1st commercial tool to support engineers to explore the block outline and block location within the chip. It would be also able to provide the recommended pin positions based on the routing connection between blocks.

Target Audience: Physical designer, CAD