Speaker: Louie De Luna

Louie De Luna is Aldec’s Chief Marketing Officer (CMO) with 20+ years’ experience in FPGA/SoC design verification and EDA tools.
He currently directs the overall product and technical marketing of Aldec’s design verification solutions. He earned his B.S. in Computer Engineering from University of Nevada, Las Vegas, in 2001.  
His practical engineering experience includes simulation-based verification, linting, CDC analysis, and hardware-assisted verification.

 

Subject: System Simulation of Versal ACAP Designs
( 最新世代超大Versal ACAP 設計的系統級模擬驗證 )

Abstract: 
Versal ACAP, developed by Xilinx/AMD, is a groundbreaking adaptable platform composed of AI Engine (AIE), Processing System (PS), Programmable Logic (PL), Network on Chip (NoC) and a wide range of hardened domain-specific IPs. Versal ACAP enables the efficient execution of complex algorithms and accelerates workloads, including machine learning, embedded computing, and high-performance computing.
In this presentation, we will introduce Versal ACAP (and discuss the different types of simulation flows and models available) and QEMU (the open-source system emulator) and its co-simulation interface with Riviera-PRO. Riviera-PRO supports system simulation of Versal ACAP designs based on the Vitis™ hardware emulation flow for testing the interactions between PL, PS and AIE.
The entire hardware emulation setup and system integration is done within the Vitis environment. It runs the AIE simulator for the graph application, Riviera-PRO’s simulator for the PL kernels, and QEMU for the PS host application. SystemC models are also available for the AIE and NoC, which can also be simulated in Riviera-PRO

 

Target Audience:SoC designers and architects, FPGA and ASIC designers, Verification, Emulation, Technical managers, Project managers