09:00~10:30

Accelion

10:30 coffee

Accelicon’s products update & EM-enhanced accurate inductor modeling and Synthesis

Dr. Albert Li

09:00~10:30

MunEDA

10:30 coffee

Efficient circuit sizing with WiCkeD for circuit analysis, modeling and optimization Dr. Volker Glöckel

10:45~11:30

Cliosoft

Design Data Collaboration Platform integrated with EDA tool Mr. Karim Khalfan

10:45~11:30

Berkeley DA

New Advances in nm Analog/ Mixed-Signal/RF IC Verification Dr. Ravi Subramanian

11:35~12:20

Edxact

Jivaro/Model Order Reduction for Parasitic & Commanche/ Parasitics data Analyzer

Mr. Daniel Borgraeve

11:35~12:20

Sagantec

Custom, analog and mixed-signal IP migration, to 40,32 and 28nm migration.

Mr. Daniel Blakely

12:20~14:00

Luxury Lunch Buffet

(12 樓八方燴西餐廳)

12:20~14:00

Luxury Lunch Buffet

(12 樓八方燴西餐廳)

14:05~14:50

Accelion

Statistical CMOS Modeling for

Variation-Aware Designs

Dr. Brian Chen

14:05~14:50

Magwel

Latch-up and TSV simulation with SNA & DevEM, Electro- thermal with PTM

Mr. Olivier Dupuis

14:55~15:40

Semitronix

Semitronix yield solutions: layout automation tools, addressable test chip design

Dr. Peter Cheng

14:55~15:40

Polyteda

Accurate, Fast &Most Scalable DRC, LVS, OPC,Verification and Model Building

Mr. Jim Cantele

15:45~16:30

CLK DA (flexible )

AOCV FX generates advanced stage-based OCV tables& Path FX analyzes critical paths for delay

15:45~16:30

Helic

(flexible)

EDA tools& solutions for GHz

and Gbps IC design extraction and modeling

Accelicon sells the leading SPICE model analysis solution for Model Quality Assurance (MQA) and SPICE model generation software (MBP). MBP allows modeling engineer to tweak and optimize SPICE model library in order to best reflect silicon data and meet designer's particular requirement for a specific type of deign. Accelicon also provides SPICE modeling service for various types of devices and process technologies.

As many mixed-signal designs migrate to 55nm and below this year, design teams are facing significant challenges in porting analog/RF IP or designing new IP in these deep nanometer nodes. These challenges include post-layout analysis, device noise analysis, mismatch analysis, and design for variability. This talk will introduce new developments in BDA's Analog FastSPICE™ Platform (AFS), is the industry’s only unified verification platform for analog, RF, and mixed-signal design.

1. SOS- The core design data collaboration platform.

2. SOS via DFII- Integrated DDM solution for Cadence Virtuoso flow.

3. SOS via ICstudio- Integrated DDM solution for Mentor ICstudio flow

4. SOS via Laker- Integrated DDM solution for SpringSoft Laker flow.

5. Visual Design Diff- Compare two versions of a schematic or layout.

AOCV FX generates advanced stage-based OCV tables that safely reduce the margin for process variation in your design – tables that work with leading static timing and optimization tools, today. Path FX

analyzes critical paths for delay, SI noise, and variance with the accuracy of SPICE and the speed and ease of use of static analysis.

Helic develops and provides EDA technology that enables rapid electromagnetic synthesis and modeling of on-chip passive devices, high-frequency interconnects, bondwires and package parasitics. Helic

technology outperform the fastest reported EM engines by 100x or more in terms of speed and capacity.

EDXACT provides technology helping layout designers to speed up the verification of design, taking parasitic effects into account. At 110nm and below,the netlist parasitics both alter the circuit behavior and slow down established simulation tools. EDXACT fills the gap between extraction and simulation tools by speeding up the flow performance without major retooling.

Magwel is the leader in 3D semiconductor-metal interconnect co- simulation and extraction solutions for ICs. It is self- consistent modeling of parasitics at the interfaces between semiconductors and metal. Unprecedented accuracy and simulation capacity with the 64-bit architec.

MunEDA´s products and solutions enable customers to reduce the design times of their circuits and to maximize robustness, reliability and yield. MunEDA´s solutions are in industrial use by leading semiconductor companies in the areas of communication computer,memories, automotive, and consumer electronics.

POLYTEDA’s PowerDRC™ and PowerLVS™ offer: Un-compromising accuracy, performance and capacity. Scalability to denser designs and process nodes beyond 28nm. Predictability of runtimes. The best defense against Over- and Under-Checking through the ability to efficiently and effectively map complex process checks into rule decks

Sagantec's solutions enable semiconductor companies to leverage their investment in existing physical design IP and accomplish dramatic savings in the implementation of custom, analog, mixed-signal and memory circuits in advanced process technologies. Automated solutions for custom IP design,proven to reduce layout time by 3x to 20x .

Semitronix provides EDA tool suites for layout automations, especially tailored for test pattern generations, data analysis and yield modeling.

We also provide industry leading addressable test chip solutions for yield enhancement and monitoring, and addressable transistor arrays which

can be used to characterize random variation caused yield loss. Our addressable test chips can be placed on MPW and scribe lines. We also provide fast parametric testers.

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